1. Field of the Invention
The present invention relates to timing-driven layout for a circuit. More particularly, the invention relates to a method of performing timing-driven layout of a circuit that uses xe2x80x9cfan-out capacitance limitation valuesxe2x80x9d of the respective functional blocks of a circuit to find the timing-error blocks in these functional blocks, which is preferably used for layout of a Large-Scale Integrated circuit (LSI).
2. Description of the Related Art
In recent years, with the rapid increase in integration scale and operation speed of LSIs, it has become extremely difficult to decrease manually the number of timing errors in a LSI layout obtained by its placement and routing processes toward zero as desired. This means that it has become extremely difficult to realize manually the desired timing error convergence. To solve this problem, timing-driven layout methods have ever been developed to make it possible to automate the timing error convergence in the layout design operation.
Generally, xe2x80x9clayout designxe2x80x9d for LSIs means the design to form and allocate desired devices and their wiring lines on a chip, which has a hierarchical structure. Specifically, the xe2x80x9clayout designxe2x80x9d includes typically the xe2x80x9cpartitioningxe2x80x9d, xe2x80x9cfloor planningxe2x80x9d, xe2x80x9cplacementxe2x80x9d, and xe2x80x9croutingxe2x80x9d processes. The usual layout design is. performed to minimize the chip area (i.e., maximize the integration level) and maximize the wiring efficiency. Unlike this, the xe2x80x9ctiming-driven layout designxe2x80x9d is performed not only to minimize the chip area (i.e., maximize the integration level) and maximize the wiring efficiency but also to satisfy the timing constraints given.
xe2x80x9cPartitioningxe2x80x9d, which is performed to decrease the complexity of overall layout, is a design process to group required gates and/or cells for a specific LSI into functional blocks to thereby divide the overall layout into xe2x80x9cin-block layoutxe2x80x9d and xe2x80x9cinter-block layoutxe2x80x9d. This facilitates the subsequent design processes.
xe2x80x9cFloor planningxe2x80x9d is a design process to determine the schematic layout (i.e., schematic xe2x80x9cin-block layoutxe2x80x9d and xe2x80x9cinter-block layoutxe2x80x9d) of the respective functional blocks formed through the partitioning process and the schematic layout of the wiring lines thereof. Due to xe2x80x9cfloor planningxe2x80x9d, the framework or skeletal structure of the LSI is determined.
xe2x80x9cPlacementxe2x80x9d is a design process to determine the location and shape of the respective functional blocks.
xe2x80x9cRoutingxe2x80x9d is a design process to determine the route or path of the wiring lines in and among the respective functional blocks.
FIG. 1 is a flowchart showing a typical example of the prior-art timing-driven layout methods of this type, which uses a timing constraint file that identifies the locations causing timing errors.
As shown in FIG. 1, in the step S101, initial placement of the functional blocks is performed based on the initial placement data. The initial placement data of the blocks are derived from the floor-planning data generated by a known method before the step S101. The routing process for wiring lines of the blocks is not performed at this stage.
In the step S102, a timing constraint file is formed by the timing constraint data generated from the initial placement data.
In the step S103, approximate propagation delay for the initial placement data is calculated.
In the step S104, it is judged whether the timing error convergence for the approximate propagation delay thus calculated is acceptable or not. If the judgment result in the step S104 is xe2x80x9cNoxe2x80x9d, the circuit configuration of the blocks and the placement thereof are corrected in the step S105 and then, the flow is returned to the step S102, repeating the steps S102 to S104. If the judgment result in the step S104 is xe2x80x9cYesxe2x80x9d, routing of the wiring lines for the blocks is performed in the step S106 and then, the wiring lines thus routed are corrected and adjusted according to the timing constraint data. The timing constraint data are generated from the timing constraint file.
In the step S108, it is judged whether the timing error convergence for the placement blocks and the routed wiring lines thus corrected and adjusted is acceptable or not. If the judgment result in the step S108 is xe2x80x9cNoxe2x80x9d, the flow is returned to the step S102, repeating the steps S102 to S104. If the result of judgment in the step S108 is xe2x80x9cYesxe2x80x9d, the flow is completed.
With the prior-art timing-driven layout method of FIG. 1, the timing constraint file (i.e., the timing constraint data) used to find the timing-error-causing locations is necessary. Thus, there is a problem that the identification behavior for the timing-error-causing locations and the content to be corrected or adjusted are largely affected by how the description of the timing constraint data is described.
Moreover, with the prior-art method of FIG. 1, wiring lengths are estimated or predicted to calculate the estimated propagation delay values and then, the timing-error-causing locations and the content for optimization are determined according to the estimated propagation delay values, Thus, some error or difference occurs between the actual wiring-induced delay values and the estimated wiring-induced delay values and as a result, there is another problem that accurate optimization is unable to be conducted.
Additionally, to eliminate the error between the actual and estimated wiring-induced delay values, the wiring lines needs to be changed or corrected after the placement and touting processes are completed. Therefore, the estimated wiring length differs from the actual wiring length and as a result, there is a possibility that timing error is not sufficiently converged as desired.
Accordingly, an object of the present invention is to provide a timing-driven layout method and a computer program product that make it possible to realize timing error convergence toward zero without any timing constraint file.
Another object of the present invention is to provide a timing-driven layout method and a computer program product that improves the timing-error convergence effect.
Still another object of the present invention is to provide a timing-driven layout method and a computer program product that makes it possible to change the circuit configuration for eliminating timing errors more correctly.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
According to a first aspect of the invention, a method of performing tinting-driven layout of a circuit is provided, which comprises the steps of:
(a) generating an initial layout result through placement of functional blocks of the circuit and routing of wiring lines for the blocks;
(b) calculating wiring capacitance values of the respective blocks using the initial layout result;
(c) Ted calculating fan-out capacitance limitation values of the respective blocks using the wiring capacitance values of the blocks calculated in the step (b);
each of the fan-out capacitance limitation values representing a maximum fan-out capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value;
(d) comparing a driving capability of each of the blocks with its fan-out capacitance limitation value, thereby generating a comparison result;
(e) defining the blocks whose driving capabilities do not exceed their fan-out capacitance limitation values as timing-error blocks based on the comparison result; and
(f) changing circuit configuration of each of the timing-error blocks based on its fan-out capacitance limitation value to decrease its propagation delay.
With the method of performing timing-driven layout of a circuit according to the first aspect of the invention, the initial layout result is generated in the step (a) through placement of functional blocks of the circuit and routing of wiring lines for the blocks. The wiring capacitance values of the respective blocks are calculated using the initial layout result generated in the step (b).
The fan-out capacitance limitation values for the respective blocks are calculated in the step (c). Each of the fan-out capacitance limitation values represents the maximum fan-out capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value.
Thereafter, the driving capability of each of the blocks is compared with its fan-out capacitance limitation value, thereby generating a comparison result in the step (d). The blocks whose driving capabilities do not exceed their fan-out capacitance limitation values are defined as the timing-error blocks based on the comparison result obtained in the step (e). Thereafter the circuit configuration of each of the timing-error blocks is changed based on its fan-out capacitance limitation value to decrease its propagation delay.
Accordingly, by repeating the steps (d) to (f) until the number of the timing-error blocks is decreased to a specific value nearby zero, timing error convergence can be realized without any timing constraint file.
Moreover, since only the circuit configuration of each of the timing-error blocks is changed in the step (f), the timing error convergence on a small value close to zero is accelerated, in other words, the timing error convergence effect is improved.
Furthermore, the initial layout result, which is generated through placement of the functional blocks of the circuit and routing of the wiring lines for the blocks in the step (a), is used for calculating the wiring capacitance values of the respective blocks in the step (b). Therefore, the change of the circuit configuration for eliminating timing errors is carried out more correctly in the step (f) than the case where estimated or predicted wiring capacitance values are used.
According to a second aspect of the invention, another method of performing timing-driven layout of a circuit is provided, which comprises the steps of:
(a) generating an initial layout result through placement of functional blocks of the circuit and routing of wiring lines for the blocks;
(b) calculating wiring capacitance values of the respective blocks using the initial layout result;
(c) calculating fan-out capacitance limitation values of the respective blocks using the wiring capacitance values of the blocks calculated in the step (b);
each of the fan-out capacitance limitation values representing a maximum fan-out capacitance value or a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value;
(d) forming a replaceable block library of replaceable functional blocks while taking their fan-out capacitance limitation values generated in the step (c) into consideration;
the replaceable blocks being divided into different block types each having a same function generated by different circuit configurations;
each of the block types having different propagation delay values and different driving capabilities;
(e) comparing a driving capability of each of the blocks with its fan-out capacitance limitation value, thereby generating a comparison result;
(f) defining the blocks whose driving capabilities do not exceed their fan-out capacitance limitation values as timing-error blocks based on the comparison result; and
(g) replacing each of the timing-error blocks with a corresponding one of the replaceable blocks having the same function to change its circuit configuration without changing its function, thereby decreasing its propagation delay.
With the method of performing timing-driven layout of a circuit according to the second aspect of the invention, approximately the same steps as those in the method according to the first aspect are carried out, except that the replaceable block library of the replaceable functional blocks is formed in the step
(d) and then, it is used for changing the circuit configuration of the timing-error blocks in the step (g).
Accordingly, there are the same advantages as those in the method of the first aspect.
According to a third aspect of the invention, still another method of performing timing-driven layout of a circuit is provided. This method comprises the same process steps as the method of the first aspect, except that (i) the initial layout result is generated through placement of functional blocks of the circuit without routing of wiring lines for the blocks, and (ii) estimated or predicted wiring capacitance values of the respective blocks are used.
Specifically, the method of the third aspect of the invention comprises the steps of:
(a) generating an initial layout result through placement of functional blocks of the circuit;
(b) estimating wiring capacitance values of the respective blocks using the initial layout result;
(c) calculating fan-out capacitance limitation values for the respective blocks using the wiring capacitance values of the blocks estimated in the step (b);
each of the fan-out capacitance limitation values representing a maximum capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value;
(d) comparing a driving capability of each of the blocks with its fan-out capacitance limitation value, thereby generating a comparison result;
(e) defining the blocks whose wiring capacitance values do not exceed their fan-out capacitance limitation values as timing-error blocks based on the comparison result; and
(f) changing circuit configuration of each of the timing-error blocks based on its fan-out capacitance limitation value to decrease its propagation delay.
With the Method of performing timing-driven layout of a circuit according to the third aspect of the invention, because of substantially the same reason as shown in the method of the first aspect, there are the same advantages as those of the method of the first aspect. However, the level of the advantages varies according to the estimation accuracy of the estimated wiring capacitance values in the step (b).
According to a fourth aspect of the invention, a further method of performing timing-driven layout of a circuit is provided. This method comprises the same process steps as the method of the second aspect, except that (i) the initial layout result is generated through placement of functional blocks of the circuit without routing of wiring lines for the blocks, and (ii) estimated or predicted wiring capacitance values of the respective blocks are used.
Specifically the method of the fourth aspect of the invention comprises the steps of:
(a) generating an initial layout result through placement of functional blocks of the circuit;
(b) estimating wiring capacitance values of the respective blocks using the initial layout result;
(c) calculating fan-out capacitance limitation values of the respective blocks using the wiring capacitance values of the blocks estimated in the step (b);
each of the fan-out capacitance limitation values representing a maximum fan-out capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value;
(d) forming a replaceable block library of replaceable functional blocks while taking their fan-out capacitance limitation values of the blocks generated in the step (c) into consideration;
the replaceable blocks being divided into different block types each having a same function generated by different circuit configurations;
each of the block types having different propagation delay values and different driving capabilities;
(a) comparing a driving capability of each of the blocks with its fan-out capacitance limitation value, thereby generating a comparison result;
(f) defining the blocks whose driving capabilities do not exceed their fan-out capacitance limitation values as timing-error blocks based on the comparison result; and
(g) replacing each of the timing-error blocks with a corresponding one of the replaceable blocks having the same function to change its circuit configuration without changing its function, thereby decreasing its propagation delay.
With the method of performing timing-driven layout of a circuit according to the fourth aspect of the invention, because of substantially the same reason as shown in the method of the second aspect, there are the same advantages as those of the method of the first aspect. However, the level of the advantages varies according to the estimation accuracy of the estimated wiring capacitance values in the step (b).
According to a fifth aspect of the present invention, a computer program product having a computer readable medium and a computer program recorded thereon is provided, the computer program being operable to perform a method of performing timing-driven layout of a circuit according to the first aspect, which is comprised of:
(a) code chat generates an initial layout result through placement or functional blocks of the circuit and routing of wiring lines for the blocks;
(b) code that calculates wiring capacitance values of the respective blocks using the initial layout result;
(c) code that calculates fan-out capacitance limitation values of the respective blocks using the wiring capacitance values of the blocks calculated in the step (b);
each of the fan-out capacitance limitation values representing a maximum fan-out capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value;
(d) code that compares a driving capability of each of the blocks with its fan-out capacitance limitation value, thereby generating a comparison result;
(e) code that defines the blocks whose driving capabilities do not exceed their fan-out capacitance limitation values as timing-error blocks based on the comparison result; and
(f) code that changes circuit configuration of each of the timing-error blocks based on its fan-out capacitance limitation value to decrease its propagation delay.
With the product according to the fifth aspect of the present invention, it is obvious that the method according to the first aspect is carried out.
According to a sixth aspect of the present invention, another computer program product having a computer readable medium and a computer program recorded thereon is provided, the computer program being operable Do perform a method of performing timing-driven layout of a circuit according to the second aspect, which is comprised of:
(a) Code that generates an initial layout result through placement of functional blocks of the circuit and routing of wiring lines for the blocks;
(b) code that calculates wiring capacitance values of the respective blocks using the initial layout result;
(c) code that calculates fan-out capacitance limitation values of the respective blocks using the wiring capacitance values of the blocks calculated in the step (b);
each of the fan-out capacitance limitation values representing a maximum fan-out capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value;
(d) code that forms a replaceable block library of replaceable functional blocks while taking their fan-out capacitance limitation values of the blocks generated in the step (c) into consideration;
the replaceable blocks being divided into different block types each having a same function generated by different circuit configurations;
each of the block types having different propagation delay values and different driving capabilities;
(e) code that compares a driving capability of each of the blocks with its fan-out capacitance limitation value, thereby generating a comparison result;
(f) code that defines the blocks whose driving capabilities do not exceed their fan-out capacitance limitation values as timing-error blocks based on the comparison result; and
(g) code that replaces each of the timing-error blocks with a corresponding one of the replaceable blocks having the same function to change its circuit configuration without changing its function, thereby decreasing its propagation delay.
With the product according to the sixth aspect of the present invention, it is obvious that the method according to the second aspect is carried out.
According to a seventh aspect of the present invention, still another computer program product having a computer readable medium and a computer program recorded thereon is provided, the computer program being operable to perform a method of performing timing-driven layout of a circuit according to the third aspect, which is comprised of:
(a) code that generates an initial layout result through placement of functional blocks of the circuit;
(b) code that estimates wiring capacitance values of the respective blocks using the initial layout result;
(c) code that calculates fan-out capacitance limitation values for the respective blocks using the wiring capacitance values of the blocks estimated in the step (b);
each of the fan-out capacitance limitation values representing a maximum capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value;
(d) code that compares a driving capability of each of the blocks with its fan-out capacitance limitation value, thereby generating a comparison result;
(e) code that defines the blocks whose wiring capacitance values do not exceed their fan-out capacitance limitation values as timing-error blocks based on the comparison result; and
(f) code that changes circuit configuration of each of the timing-error blocks based on its fan-out capacitance limitation value to decrease its propagation delay.
With the product according to the seventh aspect of the present invention, it is obvious that the method according to the third aspect is carried out.
According to an eighth aspect of the present invention, a further computer program product having a computer readable medium and a computer program recorded thereon is provided, the computer program being operable to perform a method of performing timing-driven layout of a circuit according to the fourth aspect, which is comprised of:
(a) code that generates an initial layout result through placement of functional blocks of the circuit;
(b) code that estimates wiring capacitance values of the respective blocks using the initial layout result;
(c) code that calculates fan-out capacitance limitation values of the respective blocks using the wiring capacitance values of the blocks estimated in the step (b);
each of the fan-out capacitance limitation values representing a maximum fan-out capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value;
(d) code that forms a replaceable block library of replaceable functional blocks while taking their fan-out capacitance limitation values of the blocks generated in the step (c) into consideration;
the replaceable blocks being divided into different block types each having a same function generated by different circuit configurations;
each of the block types having different propagation delay values and different driving capabilities;
(e) code that compares a driving capability of each of ;he blocks with its fan-out capacitance limitation value, thereby generating a comparison result;
(f) code that defines the blocks whose driving capabilities do not exceed their fan-out capacitance limitation values as timing-error blocks based on the comparison result; and
(g) code that replaces each of the timing-error blocks with a corresponding one of the replaceable blocks having the same function to change its circuit configuration without changing its function, thereby decreasing its propagation delay.
With the product according to the eighth aspect of the present invention, it is obvious that the method according to the fourth aspect is carried out.